The present invention relates to a field effect transistor (FET) with a sapphire substrate, in particular to a field effect transistor utilizing a group III nitride semiconductor material such as GaN.
The group III nitride semiconductors including GaN have carrier transport characteristics close to that of GaAs, together with high breakdown electric fields due to their wide band gaps. They are, thus, regarded as strong candidate materials for high frequency, high power transistors.
When a device is manufactured making use of a GaN based semiconductor material, because it is difficult to obtain a bulk GaN based substrate, there is normally employed a process for fabricating a device wherein a GaN based semiconductor layer is formed by epitaxial growth on a substrate of a different material. For the substrate of a different material, sapphire or SiC is utilized. SiC has an excellent thermal conductivity but also drawbacks of high cost and difficulty to attain a large wafer area. In contrast, although sapphire has an inferior thermal conductivity, the cost can be lowered through the use of a wafer with a larger diameter. In application, therefore, these substrates of different materials are chosen appropriately, according to the occasion and the purpose of use and so forth. In the field of MMICs (Monolithic Microwave Integrated Circuits) or the likes, there are some applications with small electric power in which the restriction for heat diffusion is not strong. In such applications, sapphire rather than SiC is in wide use.
When, using a sapphire substrate, a FET is fabricated, in prior art, a C plane sapphire is utilized and the device is formed on the C plane (Japanese Patent Application Laid-open, No. 82671/2000, Jpn. J. Appl. Phys., Vol. 38 (1999) pp. 2630 (T. Egawa et al.), etc.). FIG. 5 is a view showing a structure of a conventional MESFET (Metal Semiconductor FET) disclosed in FIG. 12 of Japanese Patent Application Laid-open, No. 82671/2000. Herein, upon a C plane sapphire substrate 51, a GaN buffer layer 52 and an n-type GaN channel layer 53 are laid, and a source electrode 54, a gate electrode 55 and a drain electrode 56 are formed thereon. Meanwhile, FIG. 6 is a view showing a structure of a conventional HEMT (High Electron Mobility Transistor) disclosed in FIG. 13 of the same publication. Upon a C plane sapphire substrate 61, a GaN buffer layer 62, an undoped GaN channel layer 63 and an n-AlGaN electron supplying layer 64 are laid, and a source electrode 65, a gate electrode 66 and a drain electrode 67 are formed thereon. In both of these cases, a GaN based semiconductor layer is laid upon a C plane of sapphire to fabricate a FET. Further, it is described, in that publication, that any plane of sapphire such as an A plane, N plane, S plane, R plane, M plane or the like may be utilized in fabricating an optical device or an electronic device with a sapphire substrate. However, examples specifically disclosed therein are nothing else but the ones of forming a device on a C plane of sapphire, and any specific processes for manufacturing or device design criteria for the cases to utilize any other plane are not described at all.
As described above, in conventional techniques, a GaN based semiconductor layer is formed upon a C plane of sapphire to form a device, which gives rise to the following problems.
First, attempts to obtain a wafer with a larger diameter are subjected to a certain restriction. In recent years, from the point of view of improving the productivity, there have been demands that wafers should have larger diameters. Yet, sapphire whose C plane is chosen as the crystal growth face cannot be readily made to have a larger diameter, because of its low workability through surface polishing due to its poor mechanical processing feasibility and little ability to grow the crystal to have a large width by the ribbon crystal method or the like. A substrate with the largest diameter attained so far is 4 inches in diameter.
Secondly, a heat radiation characteristic thereof is difficult to improve. Since sapphire has a low thermal conductivity, improvements on the heat radiation characteristic have been sought after for some time and, for this purpose, thinner substrates have been looked for. Nevertheless, sapphire has insufficient feasibility in mechanical processing as described above so that a reduction in thickness is hard to achieve and, thus, the heat radiation characteristic is difficult to improve.
Thirdly, parasitic capacitances generated in the substrate are relatively large and act as an inhibitory factor to the improvement of device performance. Especially, in the case of a C plane sapphire, it is necessary to make the substrate have a certain thickness from the point of mechanical processing feasibility, which results in generation of large parasitic capacitances in the substrate.
In light of the above problems, an object of the present invention is, in a group III nitride semiconductor device, to improve the productivity and heat radiation characteristic and, at the same time, to improve device performance through a reduction in parasitic capacitances.
The present invention relates to a semiconductor device which comprises a group III nitride semiconductor layer formed on a single crystalline sapphire substrate, a source electrode and a drain electrode formed apart from each other on the surface of said group III nitride semiconductor layer, and a gate electrode formed between said source electrode and said drain electrode; wherein
said group III nitride semiconductor layer is formed on a plane which lies parallel to a C axis of said single crystalline sapphire substrate.
The present invention provides a semiconductor device which comprises a group III nitride semiconductor layer formed on a single crystalline sapphire substrate, a source electrode and a drain electrode formed apart from each other on the surface of said group III nitride semiconductor layer, and a gate electrode formed between said source electrode and said drain electrode; wherein
said group III nitride semiconductor layer is formed on a plane lying parallel to a C axis of said single crystalline sapphire substrate; and a thickness of said single crystalline sapphire substrate is not greater than 100 xcexcm.
Further, the present invention provides a semiconductor device which comprises a group III nitride semiconductor layer formed on a single crystalline sapphire substrate, a source electrode, a drain electrode and a pad electrode formed apart from one another on the surface of said group III nitride semiconductor layer, and a gate electrode formed between said source electrode and said drain electrode; wherein
said group III nitride semiconductor layer is formed on a plane lying parallel to a C axis of said single crystalline sapphire substrate; and a thickness of said single crystalline sapphire substrate tsub satisfies the following Equation (1).                               t          sub                ≦                  10          ⁢                                                    ϵ                sub                            ⁢                              S                pad                                                                    ϵ                epi                            ⁢                              S                gate                                              ⁢                      t            act                                              (        1        )            
where
Spad is an area of the pad electrode;
Sgate is an area of the gate electrode;
xcex5sub is a relative permittivity of the sapphire substrate in the direction of the thickness;
xcex5epi is a relative permittivity of the group III nitride semiconductor layer in the direction of the thickness;
tsub is a thickness of the sapphire substrate; and
tact is an effective thickness of the group III nitride semiconductor layer.
Herein, the pad electrode refers to an electrode to supply electricity for a source or a drain from the outside. Further, tact (an effective thickness of the group III nitride semiconductor layer) represents a distance from an interface of the gate electrode and the surface of the semiconductor layer to a layer where carriers are present. For instance, in a HEMT, this refers to the distance between the lower end of the gate electrode and the two-dimensional electron gas layer, while, in a MESFET, this refers to the thickness of the depletion layer under the gate electrode.
In the present invention, as described above, a group III nitride semiconductor layer is formed on a plane lying parallel to a C axis of a single crystalline sapphire substrate and thereby a transistor is formed. A plane lying parallel to a C axis refers to an A plane, an M plane or the like of sapphire, including any plane whose offset angle with respect to one of these planes is less than 10xc2x0. Such a small angle offset does not much impair the effects of the present invention. Nevertheless, in order to attain the effects of the present invention more certainly, the offset angle is preferably set to be 5xc2x0 or less.
FIG. 4 is a view illustrating the orientation of planes of sapphire. Therein, the (0001) plane is formed perpendicular to the C axis, and the (11-20) plane and the (1-100) plane are formed parallel to the C axis. In this drawing, formed are two {0001} planes (C planes) which are equivalent to the (0001) plane, six {11-20} planes (A planes) which are equivalent to the (11-20) plane, and six {1-100} planes (M planes) which are equivalent to the (1-100) plane, respectively. Upon the afore-mentioned A plane or M plane, and more preferably upon the A plane, a group III nitride semiconductor layer is formed to construct a FET in the present invention.
In the field of optical devices such as a semiconductor laser, there are some reports in which the technique to form a group III nitride semiconductor layer upon an A plane of sapphire is examined. For a GaN based optical device, too, although a C plane of a sapphire substrate is very often chosen as the crystal growth plane for a GaN based semiconductor layer, a proposal to use an A plane of sapphire as the crystal growth plane has been put forward, as described in Japanese Patent Application Laid-open No. 297495/1995.
Nevertheless, in the field of electronic devices including FETs, no attempts of forming a device on any plane other than the C plane, in particular on a sapphire A plane, has been made, which can be attributed to the following reasons.
For a FET making use of a group III nitride semiconductor, it is important to utilize carriers generated by the piezoelectric effect and spontaneous polarization effectively, in device designing. Therefore, for growing an epitaxial layer, it becomes essential to grow an epitaxial layer by using a crystal plane where the piezoelectric effect and spontaneous polarization take place effectively, namely a C plane of the group III nitride semiconductor layer, as a growth plane. In other words, in order to form an electronic device on a plane parallel to a C axis, it becomes important to grow a group III nitride semiconductor layer stably in the direction of the C axis. Furthermore, the growth of defects in the group III nitride semiconductor layer leads to inefficient piezoelectric effects through lattice relaxation so that defects such as dislocations need to be reduced. While a reduction of defects is required in a certain extent in the case of semiconductor lasers or the like, in the case of electronic devices where the structure of semiconductor layers is considerably different, the level of the defect reduction required is quite different.
Yet, conventional techniques have not given any clear guide leading to a process for forming a group III nitride semiconductor layer stably in the direction of a C axis while reducing defects.
Under these circumstances, in the field of electronic devices, when a sapphire substrate is employed, a C plane thereof is utilized as the plane for crystal growth, and no particular attempts of forming a device on a plane other than a C plane, including an A plane of sapphire, have been made.
In the present invention, a group III nitride semiconductor layer is formed upon a plane lying parallel to a C axis of a sapphire substrate such as an A plane to construct a FET. This provides the following advantages.
First, parasitic capacitances in the longitudinal direction of the substrate can be reduced, and by the reduction of parasitic capacitances in this direction, the device capability of high-speed operation can be improved. When a plane lying parallel to a C axis is chosen as the plane for crystal growth, the relative permittivity in the direction of the substrate thickness takes the value of 9.3. This presents a reduction of about 20%, in comparison with the relative permittivity of 11.5 when a C plane is utilized as the plane for crystal growth. This leads to a marked improvement in the device capability of high-speed operation.
Secondly, the device can be manufactured using a substrate with a large diameter so that the productivity can be greatly improved. For instance, as it is possible to fabricate an A plane sapphire having a diameter as large as 8 inches or so, the productivity with the present invention can be raised much higher than that with the conventional technique utilizing a C plane sapphire.
Thirdly, particularly when an A plane sapphire is employed, as the substrate has a superior feasibility in mechanical processing, the substrate thickness can be made thinner than that with a C plane sapphire. In practice, its thickness can be made 100 xcexcm or less, even not greater than 50 xcexcm. As a result, heat diffusion characteristic of the substrate can be markedly improved and besides parasitic capacitances in the longitudinal direction of the substrate can be reduced even further.
In the present invention, when the thickness of the sapphire substrate is set to be 100 xcexcm or less, the heat diffusion characteristic of the substrate can be markedly improved and besides parasitic capacitances in the longitudinal direction of the substrate can be reduced still further.
Further, in the present invention, by setting the thickness of the sapphire substrate to satisfy the following equation:             t      sub        ≦                  1        α            ⁢                                    ϵ            sub                    ⁢                      S            pad                                                ϵ            epi                    ⁢                      S            gate                              ⁢              t        act              ,
where
Spad is the area of the pad electrode;
Sgate is the area of the gate electrode;
xcex5sub is the relative permittivity of the sapphire substrate in the direction of the thickness;
xcex5epi is the relative permittivity of the group III nitride semiconductor layer in the direction of the thickness;
tsub is the thickness of the sapphire substrate;
tact is the effective thickness of the group III nitride semiconductor layer; and
xcex1 is the coefficient,
the degradation of the FET high frequency characteristic caused by parasitic capacitances that is attributed to the pad electrodes can be suppressed. Now, referring to the drawings, the point described above is explained in detail below.
FIG. 3 is a schematic view showing a structure of a GaN based HEMT. Herein, upon a sapphire substrate 2, a GaN based semiconductor epitaxial growth layer 3 is laid and, on its surface, a gate electrode 4 and a pad electrode 5 are formed. In this figure, source and drain electrodes, interconnections and the likes are omitted.
On the back face of the sapphire substrate 2, a ground conductor layer 1 is set. The pad electrode fills the role of supplying the transistor with electric power fed from the outside. In the transistor having such a structure, parasitic capacitances C1 and C2 are generated immediately under the gate electrode 4 and immediately under the pad electrode 5, respectively, as illustrated in the figure. The amounts of C1 and C2 can be expressed as follows:                               C          2                =                                            ϵ              0                        ⁢                                                            ϵ                  sub                                ⁢                                  ϵ                  epi                                                                                                  ϵ                    epi                                    ⁢                                      t                    sub                                                  +                                                      ϵ                    sub                                    ⁢                                      t                    epi                                                                        ⁢                          S              pad                                ≈                                    ϵ              0                        ⁢                          ϵ              sub                        ⁢                                          S                pad                            /                              t                act                                                                        (        A        )                                          C          1                =                              ϵ            0                    ⁢                      ϵ            epi                    ⁢                                    S              gate                        /                          t              act                                                          (        B        )            
where
Spad is the area of the pad electrode;
Sgate is the area of the gate electrode;
xcex5sub is the relative permittivity of the sapphire substrate 2;
xcex5epi is the relative permittivity of the GaN based semiconductor epitaxial growth layer 3;
tsub is the thickness of the sapphire substrate 2;
tepi is the thickness of the GaN based semiconductor epitaxial growth layer 3; and
tact is the effective thickness of the GaN based semiconductor epitaxial growth layer 3.
While the GaN based semiconductor epitaxial growth layer is normally equal to or less than 1 xcexcm, and for instance, within 0.02 to 0.05 xcexcm in thickness, the substrate thickness is, for example, as large as 10 xcexcm so that the approximation presented in Equation (A) can be accepted. If the amount of the parasitic capacitance C2 due to the pad electrode is made to be within 10% and preferably within 5% of the amount of the parasitic capacitance C1 due to the gate electrode, degradation of high frequency characteristic for a transistor can be suppressed.
With the condition of 10% limit being taken, the contribution of the parasitic capacitance C2 becomes significant, when condition following is satisfied:
C2xe2x89xa7C1xc3x970.1 
Substituting the above Equations (A) and (B) into this equation, the following Equation (1) is given.                               t          sub                ≦                  10          ⁢                                                    ϵ                sub                            ⁢                              S                pad                                                                    ϵ                epi                            ⁢                              S                gate                                              ⁢                      t            act                                              (        1        )            
When a substrate thickness satisfying this equation is taken, the contribution of the parasitic capacitance under the pad electrode becomes significant and, thus, an application of the present invention that reduces the relative permittivity in the direction of the substrate thickness becomes even more effective. That is, aiming at success in improving heat diffusion characteristic and reducing the parasitic capacitances in the direction of the substrate thickness, it is preferable to make the substrate thickness as thin as possible. However, in conventional techniques making use of a C plane of sapphire, not only the feasibility in mechanical processing of the substrate is insufficient but also a problem of generation of the parasitic capacitance under the pad electrode may arise if a substrate thickness satisfying Equation (1) is taken so that there is a limitation to thin the substrate. In contrast, according to the present invention which reduces the relative permittivity in the direction of the substrate thickness, since the absolute value of the parasitic capacitance under the pad electrode can be lessened, the contribution of the parasitic capacitance under the pad electrode can be eliminated even if the sapphire substrate is made thin; and degradation of high frequency characteristic of the FET can be also prevented.
Herein, the values of respective parameters are normally in the following ranges.
Spad/Sgate: 10 to 1000
xcex5sub: 9.4 to 11.4
xcex5epi: approximately 9.0
tsub: 10 to 600 xcexcm (below 10 xcexcm, a faulty operation of the transistor may arise)
tact: 0.02 to 0.05 xcexcm
Taking the above ranges of the parameters into consideration, the range where the contribution of the parasitic capacitances under the pad electrode becomes significant is expressed by
tsubxe2x89xa650 xcexcm. 
Similarly, if the condition of 5% limit is taken, in the range of
tsubxe2x89xa6100 xcexcm, 
the contribution of the parasitic capacitances under the pad electrode becomes noticeable.
The above explanation is concerned with the range of the substrate thickness where the effects of the present invention become more evident, taking a HEMT as an example, but the similar holds for a MESFET. In the case of a HEMT, tact is the distance between the gate electrode and the two-dimensional electron gas layer. In the case of a MESFET, by defining tact as xe2x80x9cthe thickness of the depletion layer under the gate electrodexe2x80x9d, the similar argument to the above can be applied thereto, and thus Equation (1) is applicable to every transistor. Further, as the values of respective parameters normally employed for a MESFET are similar to those mentioned above, the range of tsub expressed by Equation (1) is also applied to every transistor.